PRODUCT

An engine that anticipates. A gateway that acts.

Two coordinated layers for closed-loop AI rack power orchestration.

DPO Engine reference control plane dashboard — simulated telemetry
01 / DPO ENGINE

Rack-level control layer that forecasts GPU load ahead of the transient and computes setpoints for the power shelf. Runs as a software process alongside the workload scheduler.

INTERFACES

  • Redfish API — telemetry ingestion
  • PMBus — power shelf control
  • OCP ORv3 PMI — rack coordination

Target: OCP certification 2027 Q4

DPO Gateway — rack-mounted hardware module with PMI-compatible form factor
02 / DPO GATEWAY

Rack-mounted hardware node that coordinates BBU discharge and PSU output inside the ORv3 power shelf. Designed as a pin-compatible replacement for the PMI module.

INTERFACES

  • OCP ORv3 PMI-compatible form factor
  • SMBus + PMBus control
  • Real-time BBU + PSU coordination

Target: UL safety certification 2027 Q4

CONTROL LOOP

How DPO responds

DPO Control-Loop Sequence
Phase 1 Rack · PSU · BBU Telemetry ingested via Redfish + PMBus
Phase 2 DPO Engine Transient forecast computed — setpoints determined
Phase 3 DPO Gateway Setpoints issued to BBU + PSU
Phase 4 Grid interface Grid sees shaped, compliant load profile
Continuous DPO Engine Compliance telemetry logged

ARCHITECTURE

Predict, orchestrate, comply.

DPO sits between the data center EMS and the ORv3 rack. The diagram below shows the DPO Gateway Specification — XMight's open contribution to OCP Rack & Power — and the closed-loop architecture our commercial DPO implements.

Designed for ORv3 / ORW racks targeting NVIDIA Blackwell-class deployments (GB200 NVL72 and successors). DPO Gateway hardware is architected to align with both the OCP Diablo 400 ±400 VDC rack standard and the NVIDIA 800 VDC MGX architecture (Huntington & Tu, 2025) — matching the dual-input compatibility pattern shown in Figure 9 of NVIDIA's published whitepaper. DPO's BBU coordination is calibrated against the 120 kW Blackwell-era envelope, with forward-compatibility to the 400 kW – 1 MW+ rack class defined by OCP Diablo 400.

DATA CENTER EMSFleet scheduler · workload orchestratorPOWER GRIDDemand · capacity · frequency schedulerDPO ENGINE — CONTROL PLANEML-driven rack-level power predictionVRT POLICYVoltage ride-through envelope enforcementPFAPR RECOVERY CONTROLPost-fault active power recovery slopeCONTROL PLANEDPO GATEWAY — SHELF PMI EXTENDRack-mounted power orchestration moduleVRT EDGE POLICYLocal VRT enforcementBBU/PSU ORCHESTRATORDischarge + output shapingRACK POWER PREDICTIONSub-ms transient forecastTELEMETRY AGGREGATORFleet data collectionAC INPUTGrid powerORv3 RACKACPOWER SHELFAC → DC conversionDPO48V DC48V DC BUSBBU SHELFStandard backupCharge ⇄ dischargeDPOBBU — VRT/FRT/PFAPRGrid compliance eventsCharge ⇄ dischargeDPOAI SERVER ×6+GPU compute load
DPO Gateway Specification — XMight's open contribution to OCP Rack & Power
THE NUMBER THAT MATTERS

Conventional ORv3 rack power reserves 20–30% headroom for transient buffering — that's compute capacity permanently locked. DPO reduces reserved headroom to 5–10% by predicting transients in millisecond windows and absorbing spikes with coordinated BBU discharge. Throttling isn't eliminated; it's made smaller, smarter, and continuous.

Source: ORv3 Base Specification headroom reservation values; DPO target band based on closed-loop simulation across reference workload mixes.

VOLTAGE EVENT RESPONSE

What happens to an ORv3 rack — with and without DPO.

Two voltage event scenarios, four traces each. Left column: conventional ORv3 rack power. Right column: same scenario with DPO coordinating BBU discharge and PSU output.

WITHOUT DPO
WITH DPO
Scenario 1 of 4 — 0.5 p.u. sag over 500 ms · Without DPONOGRR 282 VRT ENVELOPE · FAILS BOTH VRT AND PFAPR100%50%0%Vac (p.u.)100%0%PSU pwr100%0%BBU pwr100%0%48V busbar0 mssag begins≈3 msPFC trips500 msAC recovers2,500 msPFAPR limitPFAPR 2 s — FAILPFC trips → grid seesload disconnectPSU dead — restart 6–17 s≫ PFAPR 2 s budget
Scenario 1 of 4 — 0.5 p.u. sag over 500 ms · With DPODPO MEETS NOGRR 282 VRT + PFAPR100%50%0%Vac (p.u.)100%0%PSU pwr100%0%BBU pwr100%0%48V busbar0 mssag begins3–27 msDPO triggers BBU500 msAC recovers2,500 msPFAPR limitPFAPR 2 s — PASSDPO predicts → BBUdischarges → busbar heldCoordinated PSU rampmeets PFAPR recovery slope
Scenario 3 of 4 — 0.35 p.u. full AC loss · Without DPONO KEEP-ALIVE · PSU CONTROLLER DIES100%35%0%Vac (p.u.)100%0%PSU pwr100%0%BBU pwr100%0%48V busbar0 msAC fully lost≈3 msPFC trips150 msAC returns2,150 msPFAPR limitPFAPR 2 s — FAILPFC trips + controllerloses powerCold-boot 0–15 s delay≫ PFAPR 2 s — fails 5–17×
Scenario 3 of 4 — 0.35 p.u. full AC loss · With DPODPO KEEP-ALIVE · CONTROLLER SURVIVES OUTAGE100%35%0%Vac (p.u.)100%0%PSU pwr100%0%BBU pwr100%0%48V busbar0 msAC fully lost3–22 msDPO sustains busbar150 msAC returns2,150 msPFAPR limitPFAPR 2 s — PASSDPO + BBU keep busbar alivecontroller stays onlineCoordinated recoverywithin PFAPR 2 s budget

Without DPO, PFC trips within milliseconds and PSU restart consumes 6–17 seconds — far beyond the PFAPR 2-second budget. With DPO, the engine predicts the transient, the gateway coordinates BBU discharge to hold the 48V busbar, and the PSU recovers along a slope that meets PFAPR. Same hardware, rack-level control layer.

Scenarios 2 and 4 (frequency excursion and brownout) are detailed in the DPO Gateway Specification.

POWER FLOW

From GPU transient to grid-visible load.

DPO intercepts the transient before it propagates to the grid coupling point.

GPU compute
AI workload begins inference or training step — GPU draw spikes within milliseconds.
DPO Engine
Engine detects telemetry delta via Redfish + PMBus, runs MTL forecast, computes power shelf setpoints — before the transient reaches the PSU.
DPO Gateway
Gateway issues setpoints to BBU and PSU simultaneously — shaping the aggregate draw seen at the rack's grid connection point.
Grid interface
Grid sees a shaped, predictable load profile — within the envelope required for PFAPR compliance under ERCOT NOGRR 282.

INDUSTRY ANALYSIS

Four gaps that close-the-loop control must address.

Mapped against current OCP ORv3 specifications. Each gap belongs to a different leaf-spec owner — none can be closed by a single vendor or a single spec change. DPO addresses all four at rack level.

VRT GAP
01

PSU PFC low-voltage behaviour

ORv3 PSU operates 180–305 V AC; specification permits derating between 180–198 V. Below 180 V (~0.75 p.u.), PFC shuts off in approximately 20 ms with 20 ms holdup. NOGRR 282 §2.14 requires ride-through to 0 p.u.

PFAPR GAP
02

PSU controller power-on delay

PSU controller loses power on AC drop; cold-boot on restart introduces a 0–15 second random delay for inrush staggering. The PFAPR budget is 1 second — current behaviour fails by 5–17×.

COORDINATED SAG GAP
03

BBU trigger condition

BBU Module 1.4 §4.5 specifies discharge trigger at busbar < 48.5 V for 2 ms. This covers full AC loss but does not provide coordinated voltage-sag support.

PMI GAP
04

PMI interface scope

PMI Specification 1.0 §2 defines pass-through monitoring only. No write commands, no open rack-level read-write coordination path is currently defined.

DPO Engine + DPO Gateway are designed to close all four gaps at rack level, without requiring component-vendor coordination.

OCP INTEGRATION

DPO Gateway is OCP ORv3 PMI-compatible.

We identified 12 modifications required across 7 OCP spec documents for ERCOT compliance — the gap between ORv3's current disconnect-on-fault behavior and grid ride-through requirements. DPO Gateway extends PMI Specification 1.0 to enable dynamic power orchestration at the shelf level.

Specification Version ERCOT requirement Status
Open Rack V3 Base 1.0
VRTFRT
 Gap identified
Power Shelf 1.0
VRTPFAPR
 Gap identified
48V PSU 1.0
VRTPFAPRFRT
 Gap identified
PMI 1.0
VRTPFAPR
 DPO extends
BBU Shelf 1.1
VRTPFAPR
 Gap identified
BBU Module 1.4
VRTPFAPR
 Gap identified
Modbus Register Map 0.73
PFAPR
 Under review
OUR CONTRIBUTION TO OCP

The Active BBU: Dynamic Power Orchestration for Stable and Efficient ORv3 AI Racks

Presented at OCP Global Summit 2025

This paper describes the Active BBU architecture — the technical foundation of DPO — and its role in enabling PFAPR compliance while reclaiming compute headroom traditionally reserved for transient buffering.